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NXP Semiconductors /LPC43xx /CGU /PLL0USB_MDIV

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Interpret as PLL0USB_MDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MDEC0SELP0SELI0SELR

Description

PLL0USB M-divider register

Fields

MDEC

Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071.
SELP

Bandwidth select P value
SELI

Bandwidth select I value
SELR

Bandwidth select R value; SELR = 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data